1. Field of the Invention
The invention relates to a semiconductor device and, in particular, to a semiconductor device which includes a field-effect transistor (hereinafter referred to as a FET) with improved isolation.
2. Description of the Prior Art
Mobile communications equipment such as portable telephones often uses GHz-band microwaves, and their antenna switching circuits and transmitting and receiving switching circuits include switching elements for switching high-frequency signals. As an element thereof, an FET using gallium arsenide (GaAs) is often employed because high frequencies are used. Developments have been made in forming a monolithic microwave integrated circuit (MMIC) by integrating the switching circuits.
Hereinafter, an example of a conventional switch circuit device using GaAs FETs will be described. FIG. 13A shows an example of a theoretical circuit diagram of a compound semiconductor device using GaAs FETs, which is called an SPDT (Single Pole Double Throw). Sources (or drains) of first and second FET1 and FET2 are connected to a common input terminal IN, and gates of the respective FET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2, and drain (or sources) of the respective FETs are connected to first and second output terminals OUT-1 and OUT-2. Signals to be applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which an H-level signal has been applied is made to turn ON and transmits the signal applied to the input terminal IN to the corresponding output terminal. The resistors R1 and R2 are arranged for the purpose of preventing high-frequency signals from leaking via the gate electrodes to the DC potential of the control terminals Ctl-1 and Ctl-2 which are AC grounded.
FIG. 13B is a plan view when this compound semiconductor switch circuit device is integrated. As shown in the drawing, the FET1 and FET2 for switching are arranged in the central parts of a GaAs substrate, and the resistors R1 and R2 are connected to gate electrodes of the respective FETs. In addition, pads corresponding to the common input terminal IN, output terminals OUT-1 and OUT-2, and control terminals Ctl-1 and Ctl-2 are provided at the periphery of the substrate. A second-layer wiring indicated by dotted lines is a gate metal layer (Ti/Pt/Au) 68 formed simultaneously with a gate electrode formation of the respective FETs, and a third-layer wiring indicated by solid lines is a pad metal layer (Ti/Pt/Au) 77 for connection of respective elements and a pad formation. An ohmic metal layer (AuGe/Ni/Au), which is the first-layer and in ohmic contact with substrate, forms source electrodes and drain electrodes of the respective FETs, and forms electrodes at both ends of the respective resistors. This layer is not illustrated in FIG. 13 since this overlaps with the pad metal layer.
In locations where the electrode pad and the wiring are adjacent, impurity regions 60 and 61 are provided in contact with the whole lower surface (or a peripheral part) of the electrode pad and wiring. The impurity regions 60 and 61 are provided in a protruding manner from a contact part of the electrode pad or wiring to the substrate and secure a predetermined isolation.
With reference to FIG. 14A through FIG. 17C, an example of a manufacturing method for FETs, wirings and pads connected to respective terminals which are all elements of such a compound semiconductor switch circuit device will be described. Although a description will be herein given of one electrode pad, electrode pads to be connected to the above-described common input terminal, first and second control terminals, and first and second output terminals are all of an identical structure.
First step: The whole surface of a compound semiconductor substrate 51 formed of GaAs or the like is covered with a through ion implanting silicon nitride film 53 having a thickness of approximately 100 Å to 200 Å. Next, GaAs at the outermost or a predetermined region of the chip is etched to form alignment marks (unillustrated), and a photolithography process is performed to selectively open a window in a resist layer 54 above a predetermined operation layer 52. Thereafter, by use of this resist layer 54 as a mask, an ion implantation of impurity (24Mg+) to give a p−-type to select an operation layer and an ion implantation of impurity (29Si+) to give an n-type are performed for the predetermined operation layer 52. As a result, a p−-type region 55 and, an n-type operation layer 52 are formed as a two-layer structure in the non-doped substrate 51 (FIG. 14A).
Second step: The resist layer 54 used in the previous step is removed, and a photolithography process is newly performed to selectively open windows in a resist layer 58 above a predetermined source region 56, drain region 57, a predetermined wiring 62 and electrode pad 70. Subsequently, by use of this resist layer 58 as a mask, an ion implantation of impurity (29Si+) to give an n-type is performed for the substrate surface at the predetermined source region 56, the drain region 57, the predetermined wiring 62 and electrode pad 70. Thereby, an n+-type source region 56 and drain region 57 are formed, and simultaneously, n+-type regions 60 and 61 are formed on the substrate surface under the predetermined electrode pad 70 and wiring 62 (FIG. 14B).
Thereby, the wiring 62, the electrode pad 70 and the substrate 51 are separated, and no depletion layer extends to the electrode pad 70 or wiring 62, therefore, the adjacent electrode pad 70 and wiring 62 can be formed close to each other. It has been determined that setting alienation distance between the electrode pad 70 and the wiring 62 to 4 μm is sufficient to secure a 20 dB or more isolation. In addition, it has also been discovered through an electromagnetic field simulation that the isolation is as high as 40 dB at 2.4 GHz if an approximately 4 μm alienation distance is provided. Thereafter, an silicon nitride film 53 for annealing is deposited at approximately 500 Å, and activation annealing for the ion implanted p−-type region, n-type operation layer and n+-type regions is performed.
Third step: First, a photolithography process is performed to selectively open windows at parts to form a predetermined first source electrode 65 and first drain electrode 66. The silicon nitride film 53 positioned at the predetermined first source electrode 65 and first drain electrode 66 is removed by CF4 plasma, and subsequently, three layers of AuGe/Ni/Au to become an ohmic metal layer 64 are evaporated in this order. Thereafter, a resist layer 63 is removed by lift-off to leave the first source electrode 65 and first drain 66 on the source region 56 and drain region 57. Subsequently, ohmic junctions between the first source electrode 65 and source region 56 and the first drain electrode 66 and drain region 57 are formed by alloying process. (FIG. 15).
Fourth step: in FIG. 16A, a photolithography process is performed to selectively open windows at predetermined gate electrode 69, electrode pad 70, and wiring 62 parts. The silicon nitride film 53 exposed through the predetermined gate electrode 69, electrode pad 70, and wiring 62 parts is dry-etched to expose the operation layer 52 in the predetermined gate electrode 69 part and to expose the substrate 51 in the predetermined wiring 62 and predetermined electrode pad 70 parts.
An opening part of the predetermined gate electrode 69 part is provided as 0.5 μm so that a miniaturized gate electrode 69 can be formed. At this time, as described in the second step, since the nitride film under the electrode pad 70, which had conventionally been necessary to secure isolation, can be removed as a result of a provision of the n+-type regions 60 and 61, cracking of the nitride film and substrate due to an impact when a bonding wire is press-bonded is eliminated.
Next, as shown in FIG. 16B, three layers of Ti/Pt/Au are evaporated in order as a gate metal layer 68. Thereafter, a gate electrode 69, a first electrode pad 70, and wiring 62 are formed by lift-off (FIG. 16C).
Fifth step: After forming the gate electrode 69, wiring 62, and first electrode pad 70, in order to protect the operation layer 52 around the gate electrode 69, the surface of the substrate 51 is covered with a passivation film 72 made of a silicon nitride film. A photolithography process is performed on this passivation film 72 to selectively open windows in a resist for contact parts with the first source electrode 65, first drain electrode 66, gate electrode 69, and first electrode pad 70, and the passivation film 72 in these parts is dry-etched. Thereafter, the resist layer 71 is removed (FIG. 17A).
Next, a new resist layer 73 is applied to the whole surface of the substrate 51 for a photolithography process, and a photolithography process is performed to selectively open windows in the resist on a predetermined second source electrode 75, a second drain electrode 76, and a second electrode pad 77. Subsequently, three layers of Ti/Pt/Au to become a pad metal layer 74 as a third-layer electrode are evaporated in this order, whereby a second source electrode 75 and second drain electrode 76 and a second electrode pad 77, which are in contact with the first source electrode 65, first drain electrode 66, and first electrode pad 70, are formed (FIG. 17B). Since the other parts of the pad metal layer 74 are adhered onto the resist layer 73, the resist layer 73 is removed to leave only the second source electrode 75, second drain electrode 76, and second electrode pad 77 by lift-off, while the other parts are removed. Herein, since some wiring parts are formed by use of this pad metal layer 74, as a matter of course, the pad metal layer 74 of these wiring parts are left (FIG. 17C).
Furthermore, in FIG. 18 and FIG. 19, shown is a switch circuit device provided with shunt FETs for improving isolation. FIG. 18 is a circuit diagram, and FIG. 19 is a chip plan view.
In this circuit, shunt FET3 and FET4 are connected between the output terminal OUT-1 and OUT-2 of the FET1 and FET2 for switching and ground. To gates of these shunt FET3 and FET4, complementary signals of the control terminals Ctl-2 and Ctl-1 to the FET2 and FET1 are applied. As a result, when the FET1 is on, the shunt FET4 is on, and the FET2 and shunt FET3 are off.
In this circuit, when the signal path from the common input terminal IN to the output terminal OUT-1 is turned on and the signal path from the common input terminal IN to the output terminal OUT-2 is turned off, leakage of input signals to the output terminal OUT-2 is, since the shunt FET4 is on, released to the ground via a grounded capacitor C, thus isolation can be improved.
FIG. 19 shows an example of a compound semiconductor chip where such a compound semiconductor switch circuit device has been integrated.
The FET1 and FET2 for switching are arranged in the left and right central parts of a GaAs substrate 11, and the shunt FET3 and shunt FET4 are arranged in the vicinities of the left and right lower corners, and the resistors R1, R2, R3, and R4 are connected to gate electrodes 17 of the respective FETs. In addition, pads I, O1, O2, C1, C2, and G corresponding to the common input terminal IN, output terminals OUT-1 and OUT-2, control terminals Ctl-1 and Ctl-2, and ground terminal GND are provided at the periphery of the substrate. The FET1 and FET2 for switching are provided, and furthermore, source electrodes of the shunt FET3 and shunt FET4 are connected and, via a capacitor C for grounding, connected to the ground terminal GND. Moreover, second-layer wiring as shown by dotted lines is a gate metal layer 20 (Ti/Pt/Au) formed simultaneously with a gate electrode formation of the respective FETs, and third-layer wiring shown by solid lines is a pad metal layer 30 (Ti/Pt/Au) for connection of respective elements and a pad formation. An ohmic metal layer (AuGe/Ni/Au), which is in ohmic contact with the first-layer substrate, forms source electrodes and drain electrodes of the respective FETs, and forms electrodes at both ends of the respective resistors, and is not illustrated in FIG. 19 since this overlaps with the pad metal layer.
Japanese Patent Application Publication No. 2001-326501 provides the following description on a similar device.
In recent years, wireless broadband in a 2.4 GHz-band has shown a great expansion. Its transmitting rate is 11 Mbps, which is much greater than the transmitting rate of mobile telephones, and has gained popularity in ordinary households, for example, ADSL over telephone lines provides wireless service throughout an entire household, or where signals are wirelessly distributed to a cordless liquid crystal television. Recently, a 5 GHz-band has received a special attention as a next-generation wireless broadband, and furthermore, it is anticipated that its outdoor use will soon be approved as a result of revised legislation and its range of application will be greatly expanded. Compared to the 2.4 GHz band, since the 5 GHz band enables transmitting a larger amount of information at a transmission rate of 54 Mbps, there is great expectation for sending high-precision moving images without compression, etc., and development of apparatuses and construction of networks for that purpose have been eagerly carried out.
In 5 GHz-band broadband apparatuses, similar to those with a 2.4 GHz band, GaAs switch ICs are used for input/output switching and antenna switching. Since the frequency is twice that of 2.4 GHz, parasitic capacitance greatly influences deterioration in isolation. Thus, designs for improving isolation has became indispensable, such as, in a circuit using shunt FETs which have not been used in a 2.4 GHz-band switch IC, for releasing signals leaked to its OFF-side FET to its GND.
Namely, in a 5 GHz switch, it is indispensable to provide shunt FETs for an isolation improvement as shown in FIG. 18 and FIG. 19. However, provision thereof results in a great increase in chip size. In particular, when consideration is given to arranging FET3 and FET4 as shunt FETs below FET1 and FET2 of a switch circuit device of FIG. 13B, it is necessary to provide an alienation distance of 20 μm or more between the FET1 and FET2 for a switching operation and FET3 and FET4 as shunt FETs in order to secure isolation. This is because isolation must be secured between a front end part of the gate electrode 69 arranged on the operation layer of an FET and adjacent other FETs, wiring, electrode pads, and resistors as impurity regions. Herein, the front end part 69a of a gate electrode means a side opposite to where a comb-teeth-formed gate electrode 69 is bound, and this is a region where the gate electrode 69 is extended from the channel region and forms a Schottky junction with the substrate.
When high-frequency signals are applied to the wiring and electrode pad of a metal layer to form a Schottky junction with the substrate, the electric field of a depletion layer expanding in the substrate fluctuates according to the high-frequency signals. In order to prevent the high-frequency signals from leaking to an adjacent electrode and wiring at which this depletion layer arrives, for example, an electrode pad 70 part and wiring 62 are formed simultaneously with the gate electrode 69, and n+-type regions 60 and 61 are arranged in contact with the lower side of the gate electrode 68 to form a Schottky junction with the substrate and in a manner exposed from the gate metal layer 68. Thereby, expansion of the depletion layer is suppressed at the n+-type regions 60 and 61 having a Schottky junction with the gate metal layer 68, whereby the high-frequency signals are prevented from leaking.
However, at the front end part 69a of the gate electrode 69 arranged on the operation layer of a FET, this method cannot be used for an improvement in isolation from adjacent other FETs, other gate metal layers 68, and impurity regions to form resistors or other FETs. Although the front end part 69a of the gate electrode 69 is arranged on the semiconductor substrate, to arrange the n+-type regions 60 and 61 thereunder, the n+-type regions 60 and 61 require a pattern size of several μm or more because of a mask alignment error between the gate electrode 69 and n+-type regions 60 and 61 and for the reason that the n+-type regions 60 and 61 have not been formed by a fine photolithography process. Therefore, the n+-type regions 60 and 61 arranged under the adjacent gate electrode front end parts 69a come into contact with each other, and parasitic capacitance occurs between the n+-type regions 60 and 61 and the source electrode and drain electrode on the channel region of an adjacent FET. Thereby, high-frequency signals leakage between the source to drain regions via the n+-type regions 60 and 61, and this results in, if the FETs are used in a switch circuit device, a signal leakage between the input and output terminals at OFF. Therefore, there existed a problem of a deterioration in isolation of the switch circuit device.
For example, in FIG. 19, it has been necessary to secure a distance 20 μm or more between the front end part 69a of the gate electrode of the FET1 and OUT-1 pad and between the front end part 69a of the gate electrode of the FET2 and OUT-2 pad.